1. Technical Field
The present invention relates to a semiconductor integrated circuit, and in particular, to an on-die termination circuit.
2. Related Art
In recent years, due to a high operation speed of electronic devices, the swing width of a signal is reduced in order to minimize a transmission time of an interface signal between semiconductor apparatuses. As the swing width of the signal is reduced, an influence on external noise increases. That is, when a signal transmitted through a bus line having predetermined impedance passes through a bus line having different impedance, the signal may be partially reflected and then lost. This phenomenon is called impedance mismatching, and an impedance matching circuit for two bus lines is called an on-die termination (hereinafter, referred to as “ODT”) circuit.
Further, resistance may be changed due to a change in process, voltage, and temperature (hereinafter, referred to as “PVT”). Accordingly, it is important that impedance is stable regardless of the change in PVT. Therefore, during the operation of the ODT circuit, calibration is needed to make resistance uniform.
The calibration may be needed in a power-up and an initialization period during an initial operation of the semiconductor integrated circuit or in an auto-refresh period due to a change in temperature. During the calibration operation, the ODT resistor unit is repeatedly activated and inactivated while the resistance value of the ODT circuit is adjusted, thereby realizing optimum resistance. In particular, during the initial operation of the semiconductor integrated circuit, the resistance value of the ODT circuit is usually adjusted many times. Accordingly, it takes a lot of time to perform the calibration due to the repetition of activation and inactivation of the ODT resistor unit. Further, while the ODT resistor unit is repeatedly activated and inactivated, a large amount of current may be consumed.